1. Field of the Invention
The present invention relates to logic signal drivers having three-state outputs, and in particular, to logic signal drivers having three-state outputs which also generate a pre-output signal having a signal level intermediate to normal logic 0 and logic 1 signal levels.
2. Description of the Related Art
Referring to FIG. 1, a common form of logic signal driver with a pre-output drive capability typically includes a data signal driver and a pre-output circuit. A common data signal driver includes two NAND gates X1, X2, two inverters X3, X4 and totem-pole-coupled pull-up M1 and pull-down M2 MOSFETs, connected as shown. The pre-output circuit includes totem-pole-coupled pull-up M3 and pull-down M4 MOSFETs, connected as shown.
When the output enable signal OE is low (regardless of the values of the incoming complementary data signals DATA,/DATA), the outputs of the NAND gates X1, X2 (nodes 1 and 2) and inverters X3, X4 (nodes 3 and 4) will be high and low, respectively. This results in the NMOS pull-up M1 and pull-down M2 transistors being turned off, thereby causing the output signal OUT to be floating at a high impedance. When the output enable signal OE is high, the signal driver circuit is enabled for driving the output node. When both data signals DATA,/DATA are precharged to logic 0, e.g. VSS (or ground GND), the output signal OUT will be floating at a high impedance. Then, when either of the data signals, DATA,/DATA (but not both) goes high, the corresponding one of the NAND gates X1, X2 and inverters X3, X4 will turn on the corresponding pull-up transistor M1/M2, thereby causing the output signal OUT to go high or low.
The pre-output circuit (MOSFETs M3 and M4) drive the output node in response to activation of the pre-output control signal PREOUT (e.g. when the output enable signal OE is low or when both data signals DATA,/DATA are precharged low). When the pre-output control signal PREOUT is activated, i.e. high, both NMOS pre-output transistors M3, M4 are turned on, with the ratio of their relative device dimensions determining the voltage value (between VDD and VSS) of the output signal OUT. Accordingly, this results in DC current flowing (between VDD and VSS, or ground) during the generation of the pre-output signal. Further, to generate the pre-output signal, the dedicated pre-output drivers M3, M4 are required in addition to the normal output drivers M1, M2 used for outputting the normal logic signals.